This application is based upon and claims the benefit of Japanese Patent Application No. 2001-123003 filed on Apr. 20, 2001 and No. 2001-203663 filed on Jul. 4, 2001, the contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device having bipolar transistors.
U.S. Pat. No. 5,856,695 discloses a semiconductor device having NPN transistors and PNP transistors. In the semiconductor device, vertical-type transistors having an n+ burying region and p+ burying region are used as the NPN transistors and the PNP transistors in order to coincide both electrical features thereof.
However, both the n+ burying region and the p+ burying region are needed, and masks for forming the n+ burying region and the p+ burying region have to be prepared. Therefore, the manufacturing cost of the semiconductor device is increased.
Alternatively, a lateral-type transistor can be employed as the PNP transistor to avoid above-mentioned limitation. However, use of a lateral-type transistor has other associated limitations.
First, as shown in FIGS. 23A, 23B, a number of carriers are stored in an n+ base region J1 of the PNP transistor because an n+ base region J1 of the PNP transistor is wider than the p+ base region J2. Therefore, a switching speed of the PNP transistor is larger than that of the NPN transistor, thereby generating an unbalance in the switching speeds.
Second, as shown in FIG. 24, a current amplification ratio of the PNP transistor is not fixed in comparison with that of the NPN transistor. Therefore, it is difficult to use the lateral-type transistor in a complementary device.
An SOI (silicon On Insulator) substrate is often used for making a semiconductor device. The SOI substrate has a support layer, an element forming layer and a burying oxide layer that is disposed between the support layer and the element forming layer. In the semiconductor device using the SOI substrate, trenches that reach the oxide layer are provided to isolate respective semiconductor elements.
In a semiconductor device manufactured using an SOI substrate, it is possible to increase a withstanding feature with respect to noise, and to prevent parasitic diodes or transistors in the semiconductor device from activating.
As shown in FIGS. 25A, 25B, a trench 102 is formed in an element forming layer 101 for isolating respective semiconductor elements. A high impurity conductive burying diffusion region 104 is formed on a side of a burying oxide layer 103 of the element forming layer 101. A support layer 105 is disposed on the side of the burying oxide layer 103 that is opposite to the side of the element forming layer 101.
A base region 107 and a V-shaped emitter region 108 are formed in a surface region of the element forming layer 101. A collector region 109 is formed in the surface of the element forming layer 101 separately from the base region 107 and the emitter region 108.
A current flows between an emitter electrode and a collector electrode (not shown) through the burying diffusion region 104. Therefore, resistance between the emitter electrode and the collector electrode decreases, thereby ensuring required current amount.
When the burying diffusion region 104 is formed in the SOI substrate, an ion implantation is conducted from a surface of the element forming layer 101. Also, the burying oxide layer 103 is formed on a surface of the support layer 105. Thereafter, the element forming layer 101 and the support layer 105 are stacked.
Therefore, the element forming layer 101 needs a thickness corresponding to that of the burying diffusion region 104. Accordingly, the formation time of the trench 102 is typically long because the depth of the trench 102 increases depending on the thickness of the element forming layer 101.
Further, because the joint adherence between the burying oxide layer 103 and the burying diffusion region 104 is not very good, the yield ratio of the SOI substrate is low.
On the other hand, the yield ratio of the SOI substrate can be increased and manufacturing time of the SOI substrate can be shortened if the burying diffusion region 104 is removed. Further, the amount of silicon substrate can be reduced.
In this case, however, the resistance between the emitter electrode and the collector electrode will increase. As a result, the required current amount is difficult to secure.
Incidentally, the required current amount can be secured if a total area of the semiconductor device increases. However, the resulting amount of required silicon substrate cannot be reduced.
It is therefore an object of the present invention to provide a semiconductor device having bipolar transistors that is capable of obviating the above problem.
It is another object of the present invention to provide a semiconductor device having a NPN transistor and a PNP transistor having balanced electrical features.
It is a further object of the present invention to provide a semiconductor device having bipolar transistors that is capable of obtaining required current amount without requiring a burying diffusion region.
According to this invention, an NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The PNP bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in the PNP forming region. The NPN bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in an NPN forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.
Accordingly, respective features of the PNP transistor are fixed because the current flows in a longitudinal direction of the substrate. Therefore, it is possible that the semiconductor device can have the NPN transistor and the PNP transistor having balanced electrical features by using the same substrate and only one conductive type burying region.
Further, a p type well region is formed in the PNP forming region. The n type base region is formed on a surface region of the p type well region and the p type emitter region is formed on a surface region of the n type base region. A distance from a bottom portion of the p type emitter region to the p type well region in the direction perpendicular to the substrate is the shortest distance from the p type emitter region to the p type well region. Therefore, a current between the emitter region and the collector region flows in the direction perpendicular to the substrate via the bottom portion of the emitter region.
According to this invention, an n type suction region is further formed in the well region to suck carriers injected from the n type emitter region. Therefore, the holes injected from the emitter region are sucked by the suction region. As a result, the switching speed of the NPN bipolar transistor becomes high.
According to this invention, a p type diffusion region is formed in the PNP forming region for encompassing the p type collector region. Therefore, it is possible to reduce resistance around the bottom portion of the p type collector region at which a current is especially concentrated. Accordingly, it is possible to secure a high current amplification ratio HFE even if a current flowing between the p type emitter region and the collector region is high.
It is preferable that the p type collector region is formed in a center of the PNP bipolar transistor, and that the n type base region and the p type emitter region are formed around the p type collector region.
It is also preferable the p type emitter region is formed in the center of the PNP bipolar transistor, and that the n type base region and the p type collector region are formed around the p type emitter region.
It is furthermore preferable the p type collector, the n type base region and the p type emitter region are arranged in a stripe-like manner.
Further, it is preferable that the n type collector region is formed in a center of the NPN bipolar transistor, and that the p type base region and the n type emitter region are formed around the n type collector region.
It is also preferable that then type emitter region is formed in the center of the NPN bipolar transistor, and that the p type base region and the n type collector region are formed around the n type emitter region.